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Argonne National Laboratory has recently established the Distributed Supercomputing Laboratory (DSL) within its Mathematics and Computer Science Division. The DSL is both a state-of-the-art experimental facility and a focal point for research and development at the intersection of high-performance computing and networking.
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Enhancing Productivity Through World-Class Science Using World-Class Computing Facilities
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On August 25, 2006, MCS began revamping
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A project to make a network of workstations act as a distributed supercomputer. Research papers.
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"What can anyone give you greater than now"
The Berkeley Network of Workstations (NOW) project seeks to harness the
power of clustered machines connected via high-speed switched
networks. By leveraging commodity workstations and operating systems,
NOW can track industry performance increases.
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Goal: develop, implement, deploy, and evaluate mechanisms and policies to support High Throughput Computing (HTC) on large collections of distributively owned computing resources. Descriptions, documents, successes, links.
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The goal of the Condor ® Project is to develop, implement, deploy, and evaluate mechanisms and policies that support
on large collections of distributively owned computing resources. Guided by both the technological and sociological challenges of such a computing environment, the
has been
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This archive contains information about parallel I/O research.
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This archive contains information about parallel I/O research. Most of
the coverage relates to parallel file I/O.
European users please note there is a
Dictionary on Parallel Input/Output, by Heinz
Stockinger, February 1998. 223 pages.
Dealing with Massive Data: from Parallel I/O to Grid I/O ,
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Part of the Department of Electronics and Informatics of the faculty of Applied Science of the Vrije Universiteit Brussel.
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Parallel and Distributed Computing Lab of the Free University of Brussels.
We have experience in parallel discrete event simulation
using clusters (and PVM) as well as reconfigureable hardware (FPGA).
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The DOES lab strives to find and develop fundamental scientific principles in design and to facilitate their application in practice and education.
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The Design of Open Engineering Systems Lab Homepage
Welcome to the Design of Open Engineering Systems (DOES) Research Laboratory web page. Please feel free to browse through the lab member profiles to learn more about our specific research topics, or to visit the current openings page to view
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Developing a more efficient memory architecture for the HP PA 8000. Project information and papers.
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Department of Computer Science
The goal of the Avalanche project is to enable the
construction of usable and truly scalable parallel computing platforms
that are not exorbitantly expensive, yet are still capable of
achieving peta-op performance levels.
Low communication latency is the key to
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Research into program analysis, code generation, and programming tools for data-parallel languages. Technical papers.
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Welcome to the World Wide Web home page for the D System,
a research project of the Parallel Programming Systems group at
We are conducting research into program analysis, code generation, and
programming tools for data-parallel languages like High Performance Fortran.
If this research is
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The Scalable High-performance Really Inexpensive Multi-Processor project investigates how to construct high-performance servers with a network of commodity PCs and commodity operating systems. Software and research papers.
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Virtual memory-mapped communication (VMMC) was developed out of the need for a basic multicomputer communication mechanism with extremely low latency and high bandwidth. This is achieved by allowing applications to transfer data directly between two virtual memory address spaces over the network.
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Illinois Aggressive Cache-Only Memory Project. Publications and links to related projects.
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The i-acoma group at UIUC
I am graduating 2 excellent Ph.D. students, who are now looking
for a job starting Fall 2009:
Please check their resumes.
focuses on new processor, memory, and system technologies and organizations to build
novel multiprocessor computer architectures. The goal is to
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